1. Field of the Invention
The present invention relates to an inductor. More particularly, the present invention relates to an inductor used in a radio frequency integrated circuit (RFIC), and which has a multi-layer structure on the vertical and a spiral structure on the horizontal.
2. Description of the Related Art
An inductor is a passive device generally used in an RFIC. Since an inductor occupies the largest area in an RFIC, and is influenced by leakage of a substrate of the RFIC, it is difficult to obtain good leakage current characteristics for the circuit, which results in deterioration of communication quality.
Inductors also operate as passive devices used for impedance matching in RFICSs, as high quality factors of resonance tanks (L-C) that are used in voltage controlled oscillators (VCOs), and are important in reducing phase noise. However, it is difficult to manufacture an inductor having a high quality factor using a complementary metal oxide semiconductor (CMOS) process because of leakage of the substrate.
Accordingly, various methods of manufacturing inductors having a high quality factor have been studied. For example, an inductor having a high quality factor may be manufactured according to methods such as using a high resistance substrate, forming a thick oxide layer on a substrate to increase a gap between the substrate and the inductor, etching a substrate under an inductor after forming the inductor, and shielding a current from leaking into a substrate by forming a ground metal layer on the substrate.
However, each of these methods for manufacturing inductors requires an additional CMOS process, thereby increasing the cost of manufacturing the inductors.
Meanwhile, considering that the manufacturing cost of an inductor is proportional to the area thereof, an inductor that occupies the largest area in an RFIC according to the prior art presents a large cost burden.
Inductance of an inductor may be increased by increasing the turn number of the inductor. However, when this method is used, the quality factor Q of the inductor is reduced due to conductivity loss, which, combined with an effect caused by coupling the inductor to a substrate, results in reduction of the resonance frequency of the inductor, and thus the utilization range of the inductor is reduced.
For example, in a spiral inductor manufactured using a 0.18 μm CMOS process and having a width of 15 μm, a gap of 1.5 μm between wound wirings, a conductor thickness of 2 μm, and an inside diameter of 60 μm, when a turn number, or number of times the wiring is wound, is 3.5, the quality factor Q of the inductor is 6.5 in a range of 2 GHz, the inductance is 3.8 nH, and the resonance frequency is 6 GHz. However, when the turn number is increased to 7.5, although the inductance is increased to 17.6 nH, the quality factor Q is reduced to 2.5, and the resonance frequency is reduced to 3 GHz.
It is difficult to embody an inductor model fit for the physical and structural characteristics of circuit design because of effects such as coupling among conductive lines of the inductor, coupling of the conductive lines to a silicon substrate, and a lossy substrate.
FIG. 1 illustrates a general spiral inductor 10 used in an RFIC and an equivalent circuit thereof. Referring to FIG. 1, reference character LS denotes the total inductance obtained by summing a self-inductance of the spiral inductor 10 and metal inductances among metal lines of the spiral inductor. Reference character RS denotes the total resistance obtained by summing a direct current (DC) resistance of the spiral inductor 10 and an alternating current (AC) resistance affected by an ultra radio frequency skin effect. Reference character CS denotes a parasitic capacitance of a parasitic capacitor formed among the metal lines of the spiral inductor 10 and CP denotes a parasitic capacitance of a parasitic capacitor formed between the spiral inductor 10 and a silicon substrate. The parasitic capacitance CP is calculated from the thickness of an insulating layer formed between the spiral inductor 10 and the silicon substrate. Reference character RP denotes modeling of an ultra radio frequency leakage effect.
The entire quality factor Q of the equivalent circuit shown in FIG. 1 is calculated using Equation 1:
                              Q          ⁡                      (            qualityfactor            )                          =                                            MagneticEnergy              ⁡                              (                Em                )                                      -                          ElectricEnergy              ⁡                              (                Ee                )                                                          EnergyLoss            ⁡                          (              Eloss              )                                                          (        1        )            
wherein the magnetic energy (Em), the electric energy (Ee), and the energy loss (Eloss) are calculated using Equations 2, 3, and 4, respectively:
                    Em        =                                            V              2                        ⁢            ϖ            ⁢                                                  ⁢            Ls                                2            ⁡                          [                                                                    (                                          ϖ                      ⁢                                                                                          ⁢                      Ls                                        )                                    2                                +                                  Rs                  2                                            ]                                                          (        2        )                                Ee        =                                            V              2                        ⁢                          ϖ              ⁡                              (                                  Cs                  +                  Cp                                )                                              2                                    (        3        )                                Eloss        =                                            V              2                        2                    ⁡                      [                                          1                Rp                            +                              Rs                                                                            (                                              ϖ                        ⁢                                                                                                  ⁢                        Ls                                            )                                        2                                    +                                      Rs                    2                                                                        ]                                              (        4        )            
As may be seen in Equations 2, 3, and 4, as the conductor resistance RS and the parasitic capacitances CS and CP of the parasitic capacitors formed by coupling decrease, the magnetic energy (Em) increases, and the electric energy (Ee) and the energy loss (Eloss) decrease. Referring to Equation 1, in this case, the quality factor Q increases.
FIG. 2 illustrates an inductor having a horizontal multi-layer structure of the prior art. In FIG. 2, reference numeral 100 denotes a substrate, reference numerals 101 and 102 denote interlayer insulating layers, and reference character 1A denotes a lead wiring connected to first conductive layer patterns 1.
In the inductor shown in FIG. 2, the first conductive layer patterns 1 are connected to second conductive layer patterns 2 via contact holes 3. Thus, the thickness of the entire conductive layer constituting the inductor is increased, which reduces a resistance RS of the conductive layer. In addition, since a lead wiring 2A is formed under the first conductive layer patterns 1, the number of conductive layers is reduced. The lead wiring 2A is connected to one of the first conductive layer patterns 1 via a lead contact hole 3A.
FIG. 3 illustrates a spiral inductor having a vertical multi-layer structure of the prior art, which was proposed to overcome the limits of a planar structure. In FIG. 3, reference numerals 201, 205, and 207 denote first, second and third single loop type inductors, respectively. Reference numerals 202 and 203 denote an outer end and inner end of the first single loop type inductor 201, respectively. Reference numeral 204 denotes an inner end of the second single loop type inductor 205. The inner end 203 of the first single loop type inductor 201 is connected to the inner end 204 of the second single loop type inductor 205 via a cross contact 206. Reference numeral 208 denotes a vertical direction contact via connecting the second single loop type inductor 205 to the third single loop type inductor 207.
As described above, in an inductor according to the prior art, as the thickness of metal layers increases, it may be possible to expect the effect that the quality factor Q of the inductor increases. However, because of couplings between the metal layers and between the first metal layer (bottom metal layer) and the silicon substrate of the inductor of the prior art, the quality factor Q and inductance of the inductor may be reduced, and the frequency range available for the inductor may be limited.